Digital to analog converters are generally constructed of a number of switches which are selectively operated by a multi-bit digital input signal to produce corresponding currents to be summed as an analog output signal. Such digital to analog converters ordinarily are formed as integrated circuits, with each switch comprising two transistors arranged as a differential switch-pair. The individual transistors of such a switch-pair typically are controlled by complementary signal sources which operate to turn one switch ON while turning the other switch OFF. One of the two switches is coupled to a summing bus, and the other switch is coupled to a common line such as ground.
One problem with switching arrangements is that in standard CMOS logic circuits, the propagation speed of a low to high transition is different to that of a high to low transition and can be altered by the ratio of PMOS to NMOS device strengths. Unequal delay for low to high and high to low transitions from the edge of the clock signal, which causes new data to be passed into the output switch of a digital-analog converter, causes even-order distortion components in the reconstructed output waveform.
One proposed solution to this problem is illustrated in FIG. 1. As shown in FIG. 1, the circuit includes latches 10 and 20 and level shifters 30 and 40. The latch 10 receives signals D and DB from data nodes through transistors 1 and 2, respectively. The input signals D and DB are a true signal and a complementary signal, the complementary signal being present at node DB. Also, latch 20 receives signals AD and AB from data nodes through transistors 3 and 4, respectively. The input signals AD and AB are a true signal and a complementary signal, the complementary signal being present at node AB. In the first signal path, the signal D, as it is applied to latch 10, is allowed to change only during the time that the clock signal on node CLK is low. This blocks the transfer of the new data through the transistors 2 and 1, which serve as pass gates, into a static latch 10.
Transistor groups 11–14 and 21–24 form a “cross coupled inverter” latch which holds the data state while CLK is low. In the state where node S1 is high (S2 low), transistor 31 of the level shifter 30 is ON (transistor 32 is OFF) in order to connect node G2 to bias voltage VSB1. Also, transistor 33 of the level shifter 30 is ON (transistor 34 is OFF) in order to connect node G1 to a ground terminal AGND1.
Moreover, in the state where node A1 is high (A2 low), transistor 41 of the level shifter 40 is ON (transistor 42 is OFF) in order to connect node G3 to bias voltage VSB1. Also, transistor 43 of the level shifter 40 is ON (transistor 44 is OFF) in order to connect node G4 to a ground terminal AGND1.
In the state where node S1 is low (S2 high), transistor 34 is ON (transistor 33 is OFF) connecting node G1 to VSB1. Also, transistor 32 is ON (transistor 31 is OFF) connecting node G2 to AGND1.
Moreover, in the state where node A1 is low (A2 high), transistor 44 is ON (transistor 43 is OFF) connecting node G4 to VSB1. Also, transistor 42 is ON (transistor 41 is OFF) connecting node G3 to AGND1.
If the input signal D transitions from high to low while input CLK is low, when CLK transitions from low to high, the change of D from high to low arrives at node S1 before the complementary low to high change arrives at node S2. This occurrence causes transistor 31 of the level shifter 30 (and transistor 33 of the level shifter 30) to turn OFF before transistor 32 turns ON. During this time (when S1 and S2 are both low), nodes G1 and G2 are floating, and by virtue of their inherent capacitance remain at nearly the same voltage they were before.
When the low to high transition on node S2 arrives, the two transistors 32 and 34 turn ON. This causes node G2 to go to ground at exactly the same time as node G1 goes to VSB1.
If the input signal AD transitions from high to low while input CLK is low, when CLK transitions from low to high, the change of AD from high to low arrives at node A1 before the complementary low to high change arrives at node A2. This occurrence causes transistor 41 of the level shifter 40 (and transistor 43 of the level shifter 40) to turn OFF before transistor 42 turns ON. During this time (when A1 and A2 are both low), nodes G3 and G4 are floating, and by virtue of their inherent capacitance remain at nearly the same voltage they were before.
When the low to high transition on node A2 arrives, the two transistors 42 and 44 turn ON. This causes node G3 to go to ground at exactly the same time as node G4 goes to VSB1.
The propagation delay from the input CLK to the point in time when the output is switching is the same for both a 0 to 1 and a 1 to 0 change in the input D. This delay is set by the slower 0 to 1 delay through the inverters and not the faster 1 to 0 delay.
In the prior art circuit described above, the circuit uses twin data paths, one for the thermometer-coded data and an alternate path, which switches only when the other data path does not; i.e., AD switches state whenever D does not. Although this circuit provides a number of advantages; such as a data independent load to the circuit driving input CLK, the current drawn from the power supply being data independent, the disturbance on the final switch gate drive bias (VSB1) being data independent, and a more data independent disturbance on the output switch common source node; it does, however, require additional circuitry to generate the AD and AB input signals.
Therefore, it is desirable to realize a circuit that addresses the requirement for additional circuitry for the generation of these alternate inputs AD and AB. Moreover, it is desirable to create a latch that removes the need for the additional circuits while providing data independent load on the clock driver, a large source of distortion.